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1 ds05-10164-3e fujitsu semiconductor data sheet memory cmos 1 m 4 bit fast page mode dynamic ram MB814400D-60/-70 cmos 1,048,576 4 bit fast page mode dynamic ram n description the fujitsu mb814400d is a fully decoded cmos dynamic ram (dram) that contains 4,194,304 memory cells accessible in 4-bit increments. the mb814400d features a ?ast page mode of operation whereby high-speed random access of up to 1,024-bits of data within the same row can be selected. the mb814400d dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb814400d is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb814400d is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon process. this process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb814400d are not critical and all inputs are ttl compatible. n product line & features parameter MB814400D-60 mb814400d-70 ras access time 60 ns max. 70 ns max. cas access time 15 ns max. 20 ns max. address access time 30 ns max. 35 ns max. randam cycle time 110 ns min. 125 ns min. fast page mode cycle time 40 ns min. 45 ns min. low power dissipation operating current 605 mw max. 550 mw max. standby current 11 mw max. (ttl level)/5.5 mw max. (cmos level) this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 1,048,576 words 4 bit organization silicon gate, cmos, 3d-stacked capacitor cell all input and output arettl compatible 1024 refresh cycles every16.4 ms early write or oe controlled write capability ras only cas -before-ras , or hidden refresh fast page mode, read-modify-write capability on chip substrate bias generator for high performance
2 MB814400D-60/mb814400d-70 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ? to +7 v voltage of v cc supply relative to v ss v cc ? to +7 v power dissipation p d 1.0 w short circuit output current i out 50 ma storage temperature t stg ?5 to +125 c plastic soj package lcc-26p-m04 package and ordering information ?26-pin plastic (300 mil) soj, order as mb814400d-xxpjn
3 MB814400D-60/mb814400d-70 n capacitance (t a = 25 c, f = 1 mhz) parameter symbol typ. max. unit input capacitance, a 0 toa 9 c in1 ?pf input capacitance, ras , cas , we , oe c in2 ?pf input/output capacitance, dq 1 to dq 4 c dq ?pf fig. 1 ? mb814400d dynamic ram - block diagram cas ras we dq1 to dq4 oe v cc v ss clock gen #1 write clock gen mode control clock gen #2 column decoder sense ampl & i/o gate 4,194,304 bit storage cell data in buffer data out buffer address buffer pre- decoder refresh address counter row decoder substrate bias gen & a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9
4 MB814400D-60/mb814400d-70 n pin assignments and descriptions n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. parameter notes symbol min. typ. max. unit ambient operating temp spply voltage v cc 4.5 5.0 5.5 v 0 c to +70 c v ss 000 input high voltage, all inputs v ih 2.4 6.5 v input low voltage, all inputs v il ?.0 0.8 v input low voltage, dq(*) v ild ?.0 0.8 v a 0 a 1 a 2 a 3 v cc designator function 26-pin soj: 1 2 3 4 5 14 15 16 9 10 11 12 13 26 25 24 23 22 18 17 (top view) dq 1 dq 2 we ras a 9 a 8 a 7 a 6 a 5 a 4 v ss dq 4 dq 3 cas oe ras a 0 to a 9 v ss dq 1 to dq 4 we v cc oe cas data input/output write enable. row address strobe. address inputs. +5 volt power supply. output enable. column address strobe. circuit ground. 1 1 1 1
5 MB814400D-60/mb814400d-70 n functional operation address inputs twenty input bits are required to decode any four of 4,194,304 cell addresses in the memory matrix. since only ten address bits are available, the column and row inputs are separately strobed by cas and ras as shown in figure 5. first, ten row address bits are input on pins a 0 -through-a 9 and latched with the row address strobe (ras ) then, ten column address bits are input and latched with the column address strobe (cas ). both row and column ad- dresses must be stable on or before the falling edge of cas and ras , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min.)+ t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways--an early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or cas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data (dq 1 to dq 4 ) is strobed by cas and the setup/hold times are referenced to cas because we goes low before cas . in a delayed write or a read-modify-write cycle, we goes low after cas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satis?d. t cac : from the falling edge of cas when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max). t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . the data remains valid until either cas or oe returns to a high logic level. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. fast page mode of operation the fast page mode of operation provides faster memory access and lower power dissipation. the fast page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each fast page of memory, any of 1,024-bits can be accessed and, when multiple mb 814400ds are used, cas is decoded to select the desired memory fast page. fast page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted.
6 MB814400D-60/mb814400d-70 n dc characteristics (recommended operating conditions unless otherwise noted.) notes 3 parameter notes symbol conditions values unit min. typ. max. output high voltage v oh i oh = ? ma 2.4 v output low voltage v ol i ol = 4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in 5.5 v; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 m a output leakage current i dq(l) 0 v v out 5.5 v; data out disabled ?0 10 operating current (average power supply current) MB814400D-60 i cc1 ras & cas cycling; t rc = min. 110 ma mb814400d-70 100 standby current (power supply current) ttl level i cc2 ras = cas = v ih 2.0 ma cmos level ras = cas 3 v cc ?.2 v 1.0 refresh current#1 (average power supply current) MB814400D-60 i cc3 cas = v ih , ras cycling; t rc = min. 110 ma mb814400d-70 100 fast page mode current MB814400D-60 i cc4 ras = v il , cas cycling; t pc = min. 55 ma mb814400d-70 50 refresh current#2 (average power supply current) MB814400D-60 i cc5 ras cycling; cas -before-ras ; t rc = min. 110 ma mb814400d-70 100 1 1 2 2 2 2
7 MB814400D-60/mb814400d-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol MB814400D-60 mb814400d-70 unit min. max. min. max. 1 time between refresh t ref 16.4 16.4 ms 2 random read/write cycle time t rc 110 125 ns 3 read-modify-write cycle time t rwc 155 175 ns 4 access time from ras t rac 60 70 ns 5 access time from cas t cac 15 20 ns 6 column address access time t aa 30 35 ns 7 output hold time t oh 0?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time t off 15 15 ns 10 transition time t t 2 50 2 50 ns 11 ras precharge time t rp 40 45 ns 12 ras pulse width t ras 60 100000 70 100000 ns 13 ras hold time t rsh 15 20 ns 14 cas to ras precharge time t crp 5?ns 15 ras to cas delay time t rcd 20 45 20 50 ns 16 cas pulse width t cas 15 20 ns 17 cas hold time t csh 60 70 ns 18 cas precharge time (normal) t cpn 10 10 ns 19 row address set up time t asr 0?ns 20 row address hold time t rah 10 10 ns 21 column address set up time t asc 0?ns 22 column address hold time t cah 15 15 ns 23 ras to column address delay time t rad 15 30 15 35 ns 24 column address to ras lead time t ral 30 35 ns 25 column address to cas lead time t cal 30 35 ns 26 read command set up time t rcs 0?ns 27 read command and hold time referenced to ras t rrh 0?ns 28 read command and hold time referenced to cas t rch 0?ns 29 write command set up time t wcs 0?ns 30 write command hold time t wch 10 10 ns 6, 9 7, 9 8, 9 10 11, 12 18 13 14 14 15
8 MB814400D-60/mb814400d-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol MB814400D-60 mb814400d-70 unit min. max. min. max. 31 we pulse width t wp 10 10 ns 32 write command to ras lead time t rwl 15 20 ns 33 write command to cas lead time t cwl 20 20 ns 34 din set up time t ds 0?ns 35 din hold time t dh 15/18 15/18 ns 36 ras to we delay time t rwd 85 95 ns 37 cas to we delay time t cwd 40 45 ns 38 column address to we delay time t awd 55 60 ns 39 ras precharge time to cas active time (refresh cycles) t rpc 10 10 ns 40 cas set up time for cas -before-ras refresh t csr 0?ns 41 cas hold time for cas -before-ras refresh t chr 10 10 ns 42 we set up time from ras t wsr 10 10 ns 43 we hold time from ras t whr 10 10 ns 44 access time from oe t oea 15 20 ns 45 output buffer turn off delay from oe t oez 0 15 0 15 ns 46 oe to ras lead time for valid data t oel 10 10 ns 47 oe hold time referenced to we t oeh 15 20 ns 48 oe to data in delay time t oed 15 15 ns 49 din to cas delay time t dzc 0?ns 50 din to oe delay time t dzo 0?ns 51 fast page mode ras pulse width t rasp 200000 200000 ns 52 fast page mode read/write cycle time t pc 40 45 ns 53 fast page mode read-modify-write cycle time t prwc 90 95 ns 54 access time from cas precharge t cpa 35 40 ns 55 fast page mode cas precharge time t cp 10 10 ns 56 fast page mode ras hold time cas precharge t rhcp 35 40 ns 57 fast page mode cas precharge time we delay time t cpwd 60 65 ns 20 15 15 15 19 19 9 10 16 16 9, 17
9 MB814400D-60/mb814400d-70 notes: 1. referenced to v ss . 2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih , v il > ?.5 v. i cc1 , i cc3 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc4 is speci?d at one time of address change during one page cycle. 3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. 4. ac characteristics assume t t = 5 ns. 5. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min.) and v il (max.). 6. assumes that t rcd t rcd (max.) and t rad t rad (max.). if t rcd > t rcd (max.) or t rad > t rad (max.), t rac will be increased by the amount that t rcd or t rad exceeds the maximum recommended value shown in this table. refer to fig. 2 and 3. 7. if t rcd 3 t rcd (max.), t rad 3 t rad (max.), and t asc 3 t aa ?t cac ?t t , access time is t cac . 8. if t rad 3 t rad (max.) and t asc t aa ?t cac ?t t , access time is t aa . 9. measured with a load equivalent to two ttl loads and 100 pf. 10. t off and t oez is speci?d that output buffer change to high impedance state. 11. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max.) limit, access time is controlled exclusively by t cac or t aa . 12. t rcd (min.) = t rah (min.)+ 2 t t + t asc (min.). 13. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max.) limit, access time is controlled exclusively by t cac or t aa . 14. either t rrh or t rch must be satis?d for a read cycle. 15. t wcs , t rwd, t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), data out pin will remain open circuit (high impedance) through the entire cycle. if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read-modify-write cycle and data out pin will contain data read from the selected cell. if neither of the above sets of conditions is satis?d, the condition of the data out pin is indeterminated. 16. either t dzc or t dzo must be satis?d. 17. t cpa is access time from the selection of a new column address (that is caused by changing cas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max.). 18. assumes that cas -before-ras refresh. 19. assumes that test mode function. 20. if t rcd t rcd (max.), t dh = 18 ns. otherwise, t dh = 15 ns
10 MB814400D-60/mb814400d-70 n functional truth table x : ? or ? * : it is impossible in fast page mode. operation mode clock input address input data refresh note ras cas we oe row column input output standby h h x x high-z read cycle l l h l valid valid valid yes* t rcs 3 t rcs (min.) write cycle (early write) l l l x valid valid valid high-z yes* t wcs 3 t wcs (min.) read-modify- write cycle llh ? ll ? h valid valid valid valid yes* ras -only refresh cycle l h x x valid high-z yes cas -before- ras refresh cycle l l h x high-z yes t csr 3 t csr (min.) hidden refresh cycle h ? l l h l valid yes previous data is kept test mode set cycle (hidden) l l l x high-z yes t csr 3 t csr (min.) t wsr 3 t wsr (min.) test mode set cycle (cbr) h ? l l l x valid yes t csr 3 t csr (min.) t wsr 3 t wsr (min.) fig. 4 ? t cpa vs. t cp t rac (ns) t rcd (ns) t rad (ns) t cp (ns) fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad t rac (ns) t cpa (ns) 60 ns version 70 ns version 140 120 100 80 60 20 40 60 80 100 120 100 90 80 70 60 10 30 40 50 60 40 50 80 70 60 50 40 10 20 30 40 50 60 30 60 ns version 70 ns version 20 70 ns version 60 ns version
11 MB814400D-60/mb814400d-70 ? or ? row add valid data high-z high-z column add description to implement a read operation, a valid address is latched in by the ras and cas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. the access time is determined by ras (t rac ), cas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max.), access time = t cac . if t rad > t rad (max.), access time = t aa . if oe is brought low after t rac , t cac , or t aa (which ever occurs later), access time = t oea. however, if either cas or oe goes high, the output returns to a high-impedance state after t oh is satis?d. fig. 5 ? read cycle ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 9 v oh v ol dq (input) v ih v il oe t rc t ras t crp t csh t rp t rsh t cas t rcd t rad t asr t rah t asc t cah t ral t cal t oel t rrh t rch t rcs t aa t cac t oh t off t rac t dzc t on t oea t oez t dzo t oed
12 MB814400D-60/mb814400d-70 ? or ? row valid data i n add column add high-z description a write cycle is similar to a read cycle except we is set to a low state and oe is a ? or ? signal. a write cycle can be implemented in either of three ways - early write, oe write (delayed write), or read-modify-write. during all write cycles, timing parameters t rwl , t cwl and t ral must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pin is latched with the falling edge of cas and written into memory. fig. 6 ? early write cycle (oe = ? or ?? ras a 0 to a 9 cas we dq (input) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t rc dq (output) t ras t rp t csh t rsh t cas t rcd t crp t rad t asr t rah t cah t asc t ral t cal t wcs t dh t wch t ds
13 MB814400D-60/mb814400d-70 ? or ? invalid data valid data i n col row add add high-z high-z high-z description in the oe (delayed write) cycle, t wcs is not satis?d ; thus, the data on the dq pins is latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 7 ? oe (delayed write cycle) v ih v il v ih v ih v ih v il v ih v il v ih v il v ih v il ras a 0 to a 9 cas we dq (input) oe t rc v oh v ol dq (output) t ras t rp t csh t cas t rsh t rcd t crp t rad t cal t ral t cah t asc t rah t asr t cwl t rwl t wch t wp t ds t dh t off t dzc t oed t cac t aa t rac t dzo t oea t oez t oeh t oea
14 MB814400D-60/mb814400d-70 fig. 8 ? read-modify-write-cycle v ih v il v ih v il v ih v il v ih v il v oh v ol ras cas we a 0 to a 9 dq (output) ? or ? valid data i n col row add add high-z high-z valid description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. high-z v ih v il dq (input) v ih v il oe t rwc t ras t rp t csh t rcd t crp t cas t rsh t rad t asr t rah t asc t cah t ral t rwd t rcs t cwl t rwl t cwd t awd t wp t ds t dh t dzc t oed t cac t aa t rac t on t dzo t oea t oez
15 MB814400D-60/mb814400d-70 ? or ? valid data col row add add col add col add high-z high-z high-z high-z description the fast page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. fig. 9 ? fast page mode read cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il cas a 0 to a 9 we dq (input) v oh v ol dq (output) v ih v il oe t rasp t rcd t rhcp t rp t rsh t cas t cah t rrh t ral t asc t cal t cah t asc t cah t asc t asr t rah t rad t crp t pc t csh t cas t cp t rcs t rch t rcs t rch t rcs t rch t oel t dzc t cpa t dzc t dzc t dzo t oh t on t rac t cac t dzo t off t cac t oh t on t off t dzo t aa t aa t oea t oez t oea t oez t oed t oed
16 MB814400D-60/mb814400d-70 fig. 10 ? fast page mode write cycle (oe = ? or ?? v ih v il ras v ih v il v ih v il v ih v il v ih v il cas a 0 to a 9 we dq (input) v oh v ol dq (output) ? or ?l high-z valid data valid data valid data col row add add col add col add description the fast page mode write cycle is executed in the same manner as the fast page mode read cycle except the states of we and oe are reversed. data appearing on the dq pins is latched on the falling edge of cas and written into memory. during the fast page mode write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. t rasp t rhcp t rp t rsh t cas t cas t cp t pc t csh t rcd t cas t crp t cah t ral t asc t cal t cah t asc t cah t asc t rad t rah t asr t wcs t cwl t wch t wcs t cwl t cwh t wcs t wch t wcl t wp t ds t dh t dh t dh t wp t rwl t ds t wp t ds
17 MB814400D-60/mb814400d-70 fig. 11 ? fast page mode oe write cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il cas a 0 to a 9 we dq (input) v oh v ol dq (output) ? or ? invalid data col row add. add col add col add valid valid valid high-z description the fast page mode oe (delayed) write cycle is executed in the same manner as the fast page mode write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the fast page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). v ih v il oe t rad t rasp t rp t rsh t cas t cas t cp t pc t rcp t rcd t csh t cas t rah t asr t asc t cah t asc t cal t cah t asc t cah t ral t rwl t wp t cwl t cwl t cwl t rcs t wp t wp t dzc t ds t ds t ds t dh t dh t dh t aa t aa t aa t cac t oed t oed t oed t cac t oeh t cac t oeh t rac t dzo t oea t oez t oea t oez t oez t oea t oeh
18 MB814400D-60/mb814400d-70 fig. 12 ? fast page mode read-modify-write cycle v ih v il ras v ih v il v ih v il v ih v il v ih v il cas a 0 to a 9 we dq (input) v oh v ol dq (output) v ih v il oe t rad ? or ? valid data valid valid valid col row add add col add col add high-z description during fast page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input date appears at the dq pins during a normal cycle. t rasp t prwc t crp t rcd t csh t cas t cp t cas t cas t rsh t rp t ral t cah t asc t cah t asc t cah t asc t rah t asr t rcs t cwl t cpwd t cwl t rcs t wp t rcs t cwl t rwl t wp t ds t dh t wp t cwd t dzc t awd t ds t dh t ds t dh t cwd t oed t cac t aa t aa t oed t cac t on t on t oez t oeh t oez t dzo t oea t cpa t oea
19 MB814400D-60/mb814400d-70 fig. 13 ? ras -only refresh (we = oe = ? or ?? fig. 14 ? cas -before-ras refresh (addresses = oe = ? or ?? v ih v il ras v ih v il v ih v il v oh v ol cas a 0 to a 9 v ih v il v oh v ol v ih v il v ih v il ras cas we dq (output) high-z row address ? or ? description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1024 row addresses every 16.4-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and cas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, dq pin is kept in a high-impedance state. t rc t ras t rah t rpc t rp t asr t crp t off t oh high-z ? or ? description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if cas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in prep- aration for the next cas -before-ras refresh operation. we must be held high for the speci?d set up time (t wsr ) before ras goes low in order not to enter ?est mode? t rc t rp t ras t rpc t chr t csr t cpn t wsr t whr t off t oh dq (output)
20 MB814400D-60/mb814400d-70 fig. 15 ? hidden refresh cycle v ih v il ras v ih v il v ih v il v ih v il v oh v ol cas a 0 to a 9 we v ih v il v ih v il v ih v il v oh v ol v ih v il v ih v il dq (output) dq (output) oe we oe ? or ? column row address address valid data out high-z high-z valid data out high-z high-z description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of cas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. we must be held high for the speci?d set up time (t wsr ) before ras goes low in order not to enter ?est mode . dq (input) dq (input) t rc t ras t oel t ras t rp t rc t rp t crp t chr t rsh t rcd t rad t rah t ral t asr t asc t cah t rcs t rrh t wsr t whr t aa t rac t cac t dzc t off t oh t on t dzo t oea t oez t oed t rcs t rrh t wsr t whr t aa t rac t dzc t cac t on t dzo t oea t oh t off t oez t oed [test mode] [normal mode]
21 MB814400D-60/mb814400d-70 fig. 16 ? test mode set cycle (a 0 to a 9 , oe = ? or ?? v ih v il d out v ih v il v ih v il v oh v ol we cas ras description test mode ; the purpose of this test mode is to reduce device test time to one eighth of that required to test the device conventionally. the test mode function is entered by performing a we and cas -before-ras (wcbr) refresh for the entry cycle. in the test mode, read and write operations are executed in units of eights bits which are selected by the address combination of ca 0 . in the write mode, data is written into eight cells simultaneously. but the data must be input from dq 3 only. in the read mode, the data of eight cells at the selected addresses are read out from dq and checked in the following manner. when the eight bits are all ? or all ?? a ? level is output. when the eight bits show a combination of ? and ?? a ? level is output. the test mode function is exited by performing a ras -only refresh or a cas -before-ras refresh for the exit cycle. in test mode operation, the following parameters are delayed approximately 5 ns from the speci?d value in the data sheet. t rc , t rwc , t rac , t aa , t ras , t csh , t ral , t rwd , t awd , t pc , t prwc , t cpa , t rhcp , t cpwd , t rasp , t rsh , t cas , t cwd , t cac , t oea , t oed , t oeh high-z ? or ? t rc t ras t rpc t cpn t csr t chr t rpc t wsr t whr t off t oh t rp
22 MB814400D-60/mb814400d-70 fig. 17 ? cas -before-ras refresh counter test cycle parameter unit min. max. ns no. min. max. 20 15 (at recommended operating conditions unless otherwise noted.) symbol 15 ns 15 60 61 62 45 ns 40 20 ns 15 20 ns 15 MB814400D-60 mb814400d-70 access time from cas column address hold time cas to we delay time cas pulse width ras hold time note: assumes that cas -before-ras refresh counter test cycle only. v ih v il v ih v il ras cas a 0 to a 9 v ih v il v ih v il v ih v il v oh v ol v ih v il we dq (input) oe 59 58 t fcac t fcah t fcwd t fcas t frsh 62 cas precharge time t cpt 30 35 ns ? or ? valid data high-z high-z high-z valid data in column address description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the functionality of cas -before-ras refresh circuitry. if, after a cas -before-ras refresh cycle. cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are de?ed as follows: row address: bits a 0 through a 9 are de?ed by the on-chip refresh counter. column address: bits a 0 through a 9 are de?ed by latching levels on a 0 to a 9 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows ; 1) initialize the internal refresh address counter by using 8 ras only refresh cycles. 2) use the same column address throughout the test. 3) write ? to all 1024 row addresses at the same column address by using normal write cycles. 4) read ? written in procedure 3) and check; simultaneously write ? to the same addresses by using cas -before-ras refresh counter test (read-modify-write cycles). repeat this procedure 1024 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 1024 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). dq (output) t rp t chr t frsh t fcas t cpt t csr t asc t ral t fcah t wsr t whr t rcs t fcwd t cwl t rwl t wp t dh t ds t dzc t oed t fcac t on t oea t oez t dzo t oeh
23 MB814400D-60/mb814400d-70 n package dimensions (suf?: -pjn) c 1995 fujitsu limited c26054s-3c-1 lead no "a" 15.24(.600)ref 17.150.13(.675.005) 1.27(.050)typ 2.54(.100)typ 7.62 nom (.300) 8.430.13 (.332.005) index 1 5 9 13 14 18 22 26 2.25(.089)nom 0.64(.025)min r0.81(.032)typ 6.810.51 (.268.020) 0.81(.032)max 0.430.10(.017.004) details of "a" part 2.50(.098)nom 0.10(.004) * 3.40 +0.35 ?0.20 +.014 ?.008 .134 .008 ?.001 +.002 ?0.02 +0.05 0.20 26 pin, plastic soj (lcc-26p-m04) dimensions in mm(inches).
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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